This disclosure relates to self-biased phase-locked loops (SBPLLs) and more specifically, to a low jitter design for a SBPLL.
Conventional phase-locked loop (PLL) 100, shown in FIG. 1, generally includes a phase detector 102 for monitoring a phase difference between a reference signal and the feedback signal (frequency divided output signal of a voltage-controlled oscillator--VCO 108). The phase detector 102 generates an UP control signal 110 and a DOWN control signal 112 for a charge pump 114 to respectively charge and discharge a loop filter 116. The loop control voltage 118 developed across the loop filter 116 determines the output frequency of the VCO 108. The UP and DOWN control signals 110, 112 driving the charge pump 114 set the proper loop filter control voltage 118 at the input of the VCO to maintain a minimal phase error between the signals applied to the phase detector 102.
PLLs are widely used in data communications, local area networks in computer applications, microprocessors and data storage application to control data transfers. However, the rising demand for high-speed applications requires reduced clock period. As a consequence, increased accuracy of the clock frequency is requested. The clock frequency accuracy is affected by jitter. One source of jitter is the noisy environment in which PLLs must function. Another important source of jitter is the so-called `reference-feed-through jitter` or `quiet jitter`. Even when the PLL is locked there is still a small amount of phase error that determines a short pulse at the steering line of the VCO. In response to this short pulse, the VCO changes its phase. Since these pulses occur every reference cycle, the spectral component of the `quiet jitter` is the reference frequency. With a shrinking tolerance for jitter in the decreasing period of the output clock, the design of low jitter PLLs has become very challenging.
Self-biased techniques have been proposed for low-jitter PLLs in "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," John G. Maneatis, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, pp. 1723-1732, November 1996. The paper proposes a self-biased PLL "SBPLL" circuit.